Cho, Byung Jin received the B. S. degree in electrical engineering from Korea University in 1985 and the Master and Ph. D degrees in electrical engineering from KAIST, Korea, in 1987 and 1991, respectively.
From 1991 to 1993, he was with IMEC, Leuven, Belgium, as a Research Fellow, where he worked on advanced silicon processing. From 1993 to 1997, he joined the Memory R&D division of Hyundai Electronics Ind. Co. (currently Hynix Semiconductor), Korea, as a Section Manager, where he led a research team for the process development for 256M and 1G DRAM and Flash EEPROM. In 1997, he joined the Department of Electrical and Computer Engineering in the National University of Singapore (NUS), as a faculty member. He was the founder of the Silicon Nano Device Laboratory (SNDL) at NUS, and the deputy director of NUSNNI (NUS Nanoscience and Nanotechnology Initiative). Since 2007, he is with Department of Electrical Engineering in KAIST, Korea, as a faculty member. His main research interests are front-end CMOS processes including advanced gate stack and junction technologies, reliability, high mobility substrate,
advanced NVM devices, nano-scale CMOS device structures, and graphene electronics. Recently, he extended his research interests to the field of nano-energy, including thermoelectric and photo-voltaic devices. He has published over 250 technical papers and holds over 30 patents. He delivered a lot of invited talks at international conferences. He is an IEEE Senior Member since 2001.